1. Field of the Invention
The present invention relates to a semiconductor memory that utilizes variable resistance (or a change in electrical resistance) and a method of manufacturing the same.
2. Description of the Related Art
According to the increasing demand for higher storage capacity and higher operating speed of memories, the limit in making finer the structure of flash memories is becoming real at present. In such circumstances, variable resistance type storage elements which use resistance change have been proposed as a next-generation memory element technology. Examples of the variable resistance type storage element include ARAM (Atomic Random Access Memory), ReRAM (Resistance Random Access Memory), and PMC (Programmable Metallization Cell). Among these variable resistance storage elements, the ARAM is deemed as a promising technology, since it permits writing and erasing operations to be carried out at high speed (refer to, for example, Japanese Patent Laid-open No. 2006-173267 and K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shimoto, T. Tsushima, “A Novel Resistance Memory with High Scalability and Nanosecond Switching,” IEEE IEDM, pp. 783-786, 2007 as Non-patent Document 1, hereinafter).
As shown in FIG. 12, a variable resistance storage element 110 includes a combination of a pair of selection elements 111, such as transistor or diode, with a variable resistance element 112 (refer to, for example, Japanese Patent Laid-open No. 2008-072031 as Patent Document 1, hereinafter). In the case of using the system as a high-capacity memory, a plurality of the variable resistance storage elements 110 are arrayed.
For instance, as shown in an equivalent circuit diagram in FIG. 13, the variable resistance storage element 110 includes a combination of a MOS transistor 113 and a variable resistance element 112.
Now, writing and erasure of data into and from an ARAM type variable resistance storage element will be described below referring to an equivalent circuit diagram shown in FIG. 14.
As shown in FIG. 14, in the ARAM type variable resistance storage element 120, one end of a variable resistance element 122 is connected to one of diffusion layers of a MOS transistor 123. The other end of the variable resistance element 122 is grounded. In addition, the other of the diffusion layers of the MOS transistor 123 is connected to a bit line 124. Further, a word line 125 is connected to a gate electrode of the MOS transistor 123.
Besides, the variable resistance element 122 includes a storage layer which is composed of a metallic oxide film (e.g., gadolinium oxide film) and an ion supply layer which contains copper ions.
Writing and erasing operations in using the ARAM type variable resistance storage element 120 will be described below. Here, the writing operation is defined as an operation of bringing the variable resistance element 122 from a high-resistance state into a low-resistance state.
As shown in FIG. 14, a writing operation in the ARAM type variable resistance storage element 120 is carried out by impressing on the word line 125 a potential Vg such as to put the MOS transistor 123 into a conductive state and impressing a positive potential Vw on a plate line 126.
It is considered that upon this operation, from the ion supply layer that contains metallic ions, e.g., copper ions, the copper ions flow into the storage layer, to form conduction paths in the storage layer. Therefore, low-resistance regions are formed in the storage layer having been in the high-resistance state, with the result that transition from high-resistance state to low-resistance state takes place in the storage layer.
As shown in FIG. 15, erasure of data from the ARAM type variable resistance storage element 120 is carried out by a method in which a voltage Vg such as to bring the MOS transistor 123 into a conductive state is impressed on the gate through the word line 125, like in the writing operation, and simultaneously, a negative potential Ve is impressed on the plate line 126.
It is considered that upon this operation, the metallic ions, e.g., copper ions having been forming the conduction paths in the storage layer are absorbed back into the ion supply layer, so that the low-resistance regions in the storage layer vanish, and transition from low-resistance state to high-resistance state takes place in the storage layer.
In general, at the times of writing and erasing operations, the MOS transistor serving as selection transistor is in the conductive state. In this instance, therefore, the MOS transistor can be deemed as a resistance element on an equivalent basis, so that the system shown in FIG. 15 can be represented by the equivalent circuit shown in FIG. 16.
In this case, as shown in FIGS. 15 and 16, the MOS transistor 123 made finer has a resistance of several kilo-ohms to several tens of kilo-ohms. Therefore, where the resistance of the variable resistance element 122 in the low-resistance state is lower than the resistance of the MOS transistor 123, most of the potential Ve impressed on the bit line 124 undergoes voltage drop through the MOS transistor 123. This may result in that a predetermined voltage Vre is not impressed on the variable resistance element 122 and, hence, the desired erasing operation is not completed. Accordingly, a condition for ensuring a stable erasing operation is that the resistance of the variable resistance element 122 in the low-resistance state is set or controlled to be several times higher, or an order(s) of magnitude higher, than the ON resistance of the MOS transistor 123.
For example, let the ON resistance of the MOS transistor 123 be RTr, let the resistance of the variable resistance element 122 be R and let the resistance of wiring and the like be RL, then the condition for causing efficient transition of the variable resistance element 122 from low-resistance state to high-resistance state is (RTr+RL)<<R. Therefore, it is required to control the resistance R of the variable resistance element when the MOS transistor 123 is in the ON state. This resistance R is represented by an expression R=ρ(d/S), where ρ is the resistivity determined by the material of the variable resistance element 122, d is the ion conduction distance at the time of writing, and S is the cross-sectional area of the variable resistance element 122. Here, the cross-sectional area S is the area of a section of the variable resistance layer, sandwiched between the electrodes, in a plane orthogonal to the electrode-to-electrode direction. Accordingly, it may be necessary to control the resistance by regulating the cross-sectional area of the variable resistance element.
In addition, as described in Non-patent Document 1, the variable resistance element is formed at the uppermost layer of a wiring layer. Therefore, the selection transistor formed in a silicon substrate and the variable resistance element are interconnected through a plug and wiring, whereby the wiring resistance is increased. This is a major reason why it has been difficult to achieve a stable erasing operation.
Besides, Patent Document 1 discloses a structure in which an insulating film is provided with an aperture for conduction to the drain of the MOS transistor, and the aperture is filled with tungsten to form a tungsten plug. In this structure, the tungsten plug is used as a lower electrode of a variable resistance element, and a tungsten oxide layer to be a variable resistance layer is formed on the lower electrode. In this configuration, however, the variable resistance layer is formed at substantially the same level as the surface of the insulating film covering the MOS transistor. As a result, there is an enlarged distance between the MOS transistor and the variable resistance layer, leading to a raised wiring resistance. For this reason, it has been difficult to achieve a stable erasing operation.